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19-1923; Rev 1; 10/05
KIT ATION EVALU BLE AVAILA
High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
General Description
The MAX1762/MAX1791 PWM step-down controllers provide high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high-voltage batteries to generate low-voltage CPU core, I/O, and chipset RAM supplies in notebook computers and PDAs. Maxim's proprietary Quick-PWMTM pulse-width modulator is a free-running constant on-time type with input feed-forward. Its high operating frequency (300kHz) allows small external components to be utilized in PC board area-critical applications such as subnotebook computers and smart phones. PWM operation occurs at heavy loads, and automatic switchover to pulse-skipping operation occurs at lighter loads. The external high-side p-channel and low-side n-channel MOSFETs require no bootstrap components. The MAX1762/ MAX1791 are simple, easy to compensate, and do not have the noise sensitivity of conventional fixed-frequency current-mode PWMs. These devices achieve high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by their ability to drive synchronous-rectifier MOSFETs. The MAX1762/MAX1791 come in a 10-pin MAX package and offer two fixed voltages (Dual ModeTM) for each device, 1.8V/2.5V/adj (MAX1762) and 3.3V/5.0V/adj (MAX1791). High Operating Frequency (300kHz) No Current-Sense Resistor Accurate Current Limit 1% Total DC Error over Line and During Continuous Conduction Dual Mode Fixed Output 1.8V/2.5V/adj (MAX1762) 3.3V/5.0V/adj (MAX1791) 0.5V to 5.5V Output Adjust Range 5V to 20V Input Range Automatic Light-Load Pulse Skipping Operation Free-Running On-Demand PWM Foldback ModeTM UVLO PFET/NFET Synchronous Buck 4.65V at 25mA Linear Regulator Output 5A Shutdown Supply Current 230A Quiescent Supply Current 10-Pin MAX Package
Features
Ordering Information
PART MAX1762EUB MAX1791EUB TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 10 MAX
________________________Applications
Notebooks Subnotebooks Digital Cameras 1.8V/2.5V Logic and I/O Supplies Handy-Terminals PDAs Smart Phones
Pin Configuration
TOP VIEW
Typical Operating Circuit
VBATT (5V TO 20V)
VL 1 REF
VL MAX1762 MAX1791 REF FB OUT SHDN DH CS DL GND VOUT 1.8V/3.3V VP
10 VP 9 DH CS DL GND
2 3 4 5
FB OUT SHDN
MAX1762 MAX1791
8 7 6
MAX
Quick-PWM, Dual Mode, and Foldback Mode are a trademarks of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
ABSOLUTE MAXIMUM RATINGS
VP, SHDN to GND ..................................................-0.3V to +22V VP to VL ..................................................................-0.3V to +22V OUT, VL to GND .......................................................-0.3V to +6V DL, FB, REF to GND ....................................-0.3V to (VL + 0.3V) DH to GND....................................................-0.3V to (VP + 0.3V) CS to GND ....................................................-2.0V to (VP + 0.3V) REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVP = 15V, VL enabled, CVL = 1F, CREF = 0.1F, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER VP Input Voltage Range VL Input Voltage Range OUT Output Voltage (MAX1762, 1.8V Fixed) OUT Output Voltage (MAX1762, 2.5V Fixed) OUT Output Voltage (MAX1791, 3.3V Fixed) OUT Output Voltage (MAX1791, 5V Fixed) OUT Output Voltage (Adj Mode) Output Voltage Adjust Range OUT Input Resistance FB Input Bias Current Soft-Start Ramp Time On-Time (Note 2) Minimum Off-Time VL Quiescent Supply Current tON tOFF Adjustable-output mode VFB = 1.3V Zero to full ILIM VOUT = 1.25V, VVP = 6V VOUT = 5V, VVP = 6V (Note 2) FB = GND, VVL = 5V, OUT forced above the regulation point FB = GND, OUT forced above the regulation point, VVP = 20V VVL = 5V, SHDN = GND SHDN = GND, measured at VP, VVL = 0 or 5V ILOAD = 0 to 25mA, VVP = 5V to 20V 4.5 VVL = float VVL = 5V 666 2550 300 SYMBOL VVP VVL VOUT VOUT VOUT VOUT VL (overdriven) VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = GND, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = VL, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = GND, continuous conduction mode VVP = 7V to 20V, VVL = 4.75V to 5.25V, FB = VL, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = OUT, continuous conduction mode CONDITIONS MIN 5 4.75 1.773 2.463 3.250 4.925 1.231 0.5 300 -0.1 1700 740 2830 400 153 227 93 2 4 4.65 814 3110 500 260 410 A 200 15 12 4.75 A A V 800 1.8 2.5 3.3 5 1.250 TYP MAX 20 5.25 1.827 2.538 3.350 5.075 1.269 5.5 1700 0.1 UNITS V V V V V V V V k A s ns ns A
VP Quiescent Supply Current VL Shutdown Supply Current VP Shutdown Supply Current VL Output Voltage
2
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(VVP = 15V, VL enabled, CVL = 1F, CREF = 0.1F, TA = 0 to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Reference Voltage Reference Load Regulation REF Sink Current REF Fault Lockout Voltage Output Undervoltage Threshold (Foldback) Output Undervoltage Lockout Time (Foldback) Current-Limit Threshold Thermal Shutdown Threshold VL Undervoltage Lockout Threshold DH Gate Driver On-Resistance DL Gate Driver On-Resistance (Pullup) DL Gate Driver On-Resistance (Pulldown) DH Gate Driver Source/Sink Current DL Gate Driver Sink Current DL Gate Driver Source Current SHDN Logic Input High Threshold Voltage SHDN Logic Input Low Threshold Voltage VIH VIL MAX1762 VOUT = 1.8V fixed Dual Mode Threshold Voltage MAX1791 VOUT = 3.3V fixed MAX1762 VOUT = 2.5V fixed MAX1791 VOUT = 5V fixed SHDN Logic Input Current SHDN = 0 or 5V 50 2.5 -2 100 3.25 VILIM Hysteresis = 10oC Rising edge, hysteresis = 20mV, PWM disabled below this level VVP = 6V to 20V, measure at 50mA DL, high state, measure at 50mA DL, low state, measure at 50mA VDH = 3V, VVP = 6V VDL = 2.5V VDL = 2.5V 1.6 0.6 150 4 +2 4.1 5 5 1 0.6 0.9 0.5 SYMBOL CONDITIONS VVL = 4.75V to 5.25V, no load IREF = 0 to 50A REF in regulation Falling edge With respect to regulation point, no load From SHDN signal going high VOUT < 0.6 x regulation point 60 10 -90 10 1.6 70 20 -100 160 4.4 8 8 5 80 42 -110 MIN 1.98 TYP 2 MAX 2.02 0.01 UNITS V V A V % ms mV
o
MAX1762/MAX1791
C
V A A A V V mV V A
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
ELECTRICAL CHARACTERISTICS
(VVP = 15V, VL enabled, CVL = 1F, CREF = 0.1F, TA = -40 to +85C, unless otherwise noted.) (Note 1)
PARAMETER VP Input Voltage Range VL Input Voltage Range OUT Output Voltage (MAX1762, 1.8V Fixed) OUT Output Voltage (MAX1762, 2.5V Fixed) OUT Output Voltage (MAX1791, 3.3V Fixed) OUT Output Voltage (MAX1791, 5V Fixed) OUT Output Voltage (adj Mode) FB Input Bias Current On-Time (Note 2) Minimum Off-Time VL Quiescent Supply Current VP Quiescent Supply Current VL Shutdown Supply Current VP Shutdown Supply Current VL Output Voltage Reference Voltage Reference Load Regulation REF Sink Current Output Undervoltage Threshold (Foldback) Output Undervoltage Lockout Time (Foldback) Current-Limit Threshold VILIM tON tOFF SYMBOL VVP VVL VOUT VOUT VOUT VOUT VL (overdriven) VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = GND, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = VL, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = GND, continuous conduction mode VVP = 7V to 20V, VVL = 4.75V to 5.25V, FB = VL, continuous conduction mode VVP = 5V to 20V, VVL = 4.75V to 5.25V, FB = OUT, continuous conduction mode VFB = 1.3V VOUT = 1.25V, VVP = 6V VOUT = 5V, VVP = 6V (Note 2) FB = GND, VVL = 5V, OUT forced above the regulation point FB = GND, OUT forced above the regulation point VVP = 20V VVL = 5V, SHDN = GND SHDN = GND, measured at VP, VVL = 0 or 5V ILOAD = 0 to 25mA, VVP = 5V to 20V VVL = 4.75V to 5.25V, no load IREF = 0 to 50A REF in regulation With respect to regulation point, no load From SHDN signal going high, VOUT < 0.6 x regulation point 10 60 10 -90 80 42 -110 4.5 1.98 VVL = float VVL = 5V CONDITIONS MIN 5 4.75 1.773 2.463 3.250 4.925 1.231 -0.2 666 2550 250 TYP MAX 20 5.25 1.827 2.538 3.350 5.075 1.269 0.2 814 3110 550 260 410 200 15 12 4.75 2.02 0.01 UNITS V V V V V V V A ns ns A A A A V V V A % ms mV
4
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks
ELECTRICAL CHARACTERISTICS (continued)
(VVP = 15V, VL enabled, CVL = 1F, CREF = 0.1F, TA = -40 to +85C, unless otherwise noted.) (Note 1)
PARAMETER VL Undervoltage Lockout Threshold SHDN Logic Input High Threshold Voltage SHDN Logic Input Low Threshold Voltage VIH VIL MAX1762 VOUT = 1.8V fixed Dual Mode Threshold Voltage MAX1791 VOUT = 3.3V fixed MAX1762 VOUT = 2.5V fixed MAX1791 VOUT = 5V fixed 50 2.5 SYMBOL CONDITIONS Rising edge, hysteresis = 20mV, PWM disabled below this level MIN 4.1 1.6 0.6 150 4 TYP MAX 4.4 UNITS V V V mV V
MAX1762/MAX1791
Note 1: Specifications to -40C are guaranteed by design, not production tested. Note 2: One-shot times are measured at the DH pin (VP = 15V, CDH = 400pF, 90% point to 90% point; see drawing below for measurement details).
tON DH 90% 90%
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX1762 EFFICIENCY vs. LOAD (2.5V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 1000 10,000 LOAD CURRENT (mA) VVP = 18V VVP = 12V VVP = 7V VVP = 5V
MAX1762/91 toc01
MAX1762 EFFICIENCY vs. LOAD (1.8V)
MAX1762/91 toc02
MAX1762 EFFICIENCY vs. LOAD (1V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VVP = 12V VVP = 18V VVP = 7V VVP = 5V
MAX1762/91 toc03
100
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 VVP = 7V
VVP = 5V
100
VVP = 12V VVP = 18V
10
100
1000
10,000
0.1
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
MAX1791 EFFICIENCY vs. LOAD (5V)
MAX1762/91 toc04
MAX1791 EFFICIENCY vs. LOAD (3.3V)
MAX1762/91 toc05
MAX1791 EFFICIENCY vs. LOAD (3.0V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VVP = 18V VVP = 12V VVP = 7V VVP = 5V
MAX1762/91 toc06
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 100 1000 VVP = 12V VVP = 18V VVP = 7V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VVP = 7V VVP = 18V VVP = 12V VVP = 5V
100
10,000
0.1
1
10
100
1000
10,000
0.1
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FREQUENCY vs. SUPPLY VOLTAGE
MAX1762/91 toc07
VL VOLTAGE ERROR vs. OUTPUT CURRENT
VVP = 12V VOUT = 2.5V
MAX1762/91 toc08
375 VOUT = 3.3V 350 FREQUENCY (kHz) VOUT = 5.0V 325 VOUT = 2.5V
0.1 0 VL VOLTAGE ERROR (%) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6
300
275 VOUT = 1.8V 250 5 LOAD = 1A 8 11 14 17
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
VL CURRENT (mA)
6
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE (SHUTDOWN)
MAX1762/91 toc09
SUPPLY CURRENT vs. INPUT VOLTAGE
300 250 SUPPLY CURRENT (A) 200 150 100 50 0 5 8 11 VP (V) 14 17 VOUT = 3.3V NO LOAD 6.0 5.8 5.6 SUPPLY CURRENT (A) 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0
NO LOAD
5
8
11 VP (V)
14
17
LINE-TRANSIENT RESPONSE
MAX1762/91 toc11
LOAD-TRANSIENT RESPONSE
MAX1762/91 toc12
LOAD-TRANSIENT RESPONSE
MAX1762/91 toc13
MAX1762/91 toc10
VP 1V/div 7V
VOUT AC-COUPLED 100mV/div
VOUT AC-COUPLED 100mV/div
VOUT AC-COUPLED 20mV/div
IL 2A/div
ILOAD 2A/div
100s/div VVP = 7.5V TO 8V, ILOAD = 0, VOUT = 2.5V
100s/div VVP = 12V, IL = 0 TO 2A, VOUT = 2.5V
100s/div VVP = 12V, ILOAD = 0 TO 2A, VOUT = 1.8V
OUTPUT OVERLOAD WAVEFORMS
MAX1762/91 toc14
SHUTDOWN AND STARTUP WAVEFORMS (IL = 300mA)
MAX1762/91 toc15
SHUTDOWN AND STARTUP WAVEFORMS (IL = 2.5A)
MAX1762/91 toc16
VOUT AC-COUPLED
SHDN 5V/div
SHDN 5V/div
VOUT 2V/div ILOAD 2A/div
VOUT 2V/div
ILX 1A/div
ILX 2A/div
100s/div VVP = 12V, ILOAD = 0 TO 3A, VOUT = 2.5V
2ms/div VVP = 8V, ILOAD = 300mA, VOUT = 2.5V
2ms/div VVP = 8V, ILOAD = 2.5A, VOUT = 2.5V
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Pin Description
PIN 1 NAME VL FUNCTION +4.65V Linear Regulator Output. Serves as the supply input for the DL gate driver and supplies up to 25mA to external loads. VL can be overdriven using an external 5V supply. Bypass VL to GND with at least a 1F ceramic capacitor. 2V Reference Voltage Output. Bypass to GND with 0.1F ceramic capacitor. REF can deliver up to 50A for external loads. Feedback Input. Connect to an external resistive divider from OUT to GND in adjustable version. Regulates to 1.25V. FB also serves as Dual Mode select pin. Connect FB to GND for a fixed 1.8V (MAX1762) or 3.3V (MAX1791) output, or to VL for a fixed 2.5V (MAX1762) or 5.0V (MAX1791) output. Output Voltage Connection. OUT is used for sensing the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. Shutdown Input. Connect to a voltage less than VIL (<0.6V) to shut down the device. Connect to a voltage greater than VIH (>1.6V) for normal operation. Analog and Power Ground Low-Side Gate Driver Output. DL swings between VL and GND. Current-Sense Connection. For lossless current sensing, connect CS to the junction of the MOSFETs and inductor. For more accurate current sensing, connect CS to a current-sense resistor from the source of the low-side switch to GND. High-Side Gate Driver Output. DH swings between VP and GND. Battery Voltage Supply Input. Used for PWM one-shot timing and as the input for the VL regulator and DH gate drivers.
2
REF
3
FB
4 5 6 7 8 9 10
OUT SHDN GND DL CS DH VP
Standard Application Circuit
The standard application circuit (Figure 1) generates a low-voltage output for general-purpose use in notebook computers (I/O supply, fixed CPU, core supply, and DRAM supply). This DC-DC converter steps down battery voltage from 5V to 20V with high efficiency and accuracy to a fixed voltage of 1.8V/2.5V/adj (MAX1762) or 3.3V/5.0V/adj (MAX1791). Both the MAX1762 and MAX1791 can be configured for adjustable output voltages (VOUT > 1.25V), using a resistive voltage-divider from VOUT to FB to adjust the output voltage (Figure 2). Similarly, Figure 3 shows an application circuit for VOUT < 1.25V, where a resistive voltage-divider from REF to FB is used to set the output voltage. Figure 4 shows how to set the regulator's current limit with an external sense resistor from CS to GND. Table 1 lists the components for each application circuit, and Table 2 contains contact information for the component manufacturers.
Detailed Description
The MAX1762/MAX1791 step-down controllers are targeted at low-voltage chipsets and RAM power supplies for notebook and subnotebook computers, with additional applications in digital cameras, PDAs, and handy-terminals. Maxim's proprietary Quick-PWM pulse-width modulator (Figure 5) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency (300kHz) over a wide range of input voltages (5V to 20V). The MAX1762 has fixed 1.8V or 2.5V outputs, while the MAX1791 has fixed 3.3V or 5.0V output voltages. Using an external resistive divider, VOUT can be set between 0.5V and 5.5V on either device. Quick-PWM architecture circumvents the poor load-transient response of fixed-frequency current-mode PWMs. This type of design avoids the problems commonly encountered with conventional constant-on-time and constant-offtime PWM schemes.
8
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
VVP C1 10F C2 1F VL VP 10 1F
MAX1762 MAX1791
C3 0.1F REF FB OUT SHDN DH CS DL GND
Q1
L1 7H C4 220F
VOUT
Q2
Figure 1. Typical Application Circuit for Fixed Voltage
VVP C1 10F C2 1F VL VP 10 1F
MAX1762 MAX1791
C3 0.1F REF FB OUT SHDN DH CS DL GND
Q1
L1 7H C4 220F
VOUT R1
Q2
R2
Figure 2. Typical Application Circuit for Adjustable Output VOUT > 1.25V
VVP C1 10F C2 1F VL VP 10 1F DH
MAX1762 MAX1791
REF C3 0.1F R1 FB R2 OUT SHDN DL GND CS
Q1 L1 7H C4 220F
VOUT
Q2
Figure 3. Typical Application Circuit for VOUT < 1.25V _______________________________________________________________________________________ 9
High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
VVP C1 10F C2 1F VL VP 10
MAX1762 MAX1791
REF C3 0.1F FB DH CS
1F
Q1
L1 10H C4 150F
VOUT
OUT
DL
Q2
RS SHDN GND
Figure 4. Operation with External Current-Sense Resistor
Table 1. Component Selection for Standard Applications
COMPONENT Input Voltage Range Inductor (H) L1 Inductor Q1 MOSFETS C1 Input Capacitor C2 VL Cap C3 REF Cap C4 Output Cap 1.8V/2.5V/3.3V/5.0V AT 2A 5V to 20V 7 CDRH104-7R0NC Sumida NDS8958A Fairchild TMK432BJ106KM Taiyo Yuden EMK3160J105KL Taiyo Yuden UMK316BI104KH Taiyo Yuden 10TPB220M Sanyo 1V AT 2A 5V to 20V 5.2 CDRH104-5R2NC Sumida SI4539ADY Fairchild TMK432BJ106 Taiyo Yuden LMK316BJ475 Taiyo Yuden UMK316BI104KH Taiyo Yuden 6TPB150M Sanyo
10
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Table 2. Component Manufacturers
MANUFACTURER Coiltronics Fairchild Semiconductor Sanyo USA Sumida Japan Taiyo Yuden 81-3-3607-5111 408-573-4150 www.t-yuden.com 561-241-7876 408-822-2181 619-661-6835 847-956-0666 www.sumida.com USA PHONE WEBSITE INFO www.coiltronics.com www.fairchildsemi.com www.secc.co.jp
VP VP ON-TIME COMPUTE OUT Q TRIG Q 1-SHOT S Q R S Q R CS VL CVL LINEAR REG REF REF -30% ON/OFF CONTROL TIMER 2V VREF UVP LATCH OUT FEEDBACK MUX (FIGURE 9) FB VL DL DL ILIM VOS -100mV TOFF TON DH DH 1F
10 VIN CIN Q1
DRIVER
TON TRIG Q 1-SHOT VP
SHDN
OUT COUT Q2
VP
DRIVER GND
REF CREF
MAX1762 MAX1791
OUT
FB
Figure 5. Functional Diagram
VP Input and VL Logic Supply
An internal linear regulator supplied by VP produces the +4.65V supply (VL) that powers the PWM controller, logic, reference, and other blocks within the MAX1762/MAX1791. This +4.65V low-dropout linear regulator can supply up to 25mA for external loads. Bypass VL to GND with at least a 1F ceramic capacitor. VVP can range between 5V and 20V. VL is turned
off when the device is in shutdown and drops by approximately 500mV during a fault condition, such as when the output is short circuited to ground, and recovers when SHDN is cycled or power is reset. If VL is not driven externally, then V VP should be at least 5V to ensure operation. If VVP is running from a 5V (10%) supply, V VP should be externally connected to VL.
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Overdriving the VL regulator with an external 5V supply also increases the MAX1762/MAX1791s' efficiency. The MAX1762/MAX1791 include an input undervoltage lockout (UVLO) circuit that prevents the device from switching until VL > 4.4V (max). UVLO ensures there is a sufficient drive for the external MOSFETs, prevents the high-side MOSFET from being turned on for near 100% duty cycle, and keeps the output in regulation. adjustable 0.5s (max) minimum off-time. Worst-case dropout performance is determined by the minimum on-time spec. The worst-case duty factor limit is: t ON MIN
t ON MIN + t OFF MAX
()
()
()
=
2.55s 2.55s+0.5s
= 84%
Voltage Reference (REF)
The 2V reference (REF) is accurate to 1% over temperature, making REF useful as a precision system reference. Bypass REF to GND with a 0.1F (min) ceramic capacitor. REF can supply up to 50A for external loads. However, if tight-accuracy specs for either VOUT or REF are essential, avoid loading REF. Loading slightly reduces the main output voltage by an amount that tracks the reference-voltage load regulation error.
with VBATT = 6V and VOUT = 5V. Therefore, with IR voltage drops in the loop included, the minimum input voltage to achieve VOUT = 5V is about 6.1V, using the step-down transfer function equation for duty cycle (DC = VOUT/VIN). Typical units exhibit better performance. Note that transient response is somewhat degraded near dropout, and the circuit may need additional bulk output capacitance to support fast load changes.
Automatic Pulse-Skipping Switchover
This PWM control algorithm automatically switches over to pulse-skipping operation at light loads. The MAX1762/MAX1791 truncates the low-side switch's ontime when the inductor current drops to zero. The load current level at which pulse-skipping/PWM crossover occurs is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 6): ILOAD(SKIP) = K x VOUT 2L VVP - VOUT VVP
Free-Running Constant On-Time PWM Controller with Input Feed-Forward
The PWM control architecture is a quasi-fixed-frequency constant on-time current-mode type with voltage feed-forward. This architecture relies on the output ripple voltage to provide the PWM ramp signal; thus, the output filter capacitor's ESR acts as a feedback resistor. The control algorithm is very simple. The high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. There is another one-shot that sets a minimum amount of offtime (500ns max). The on-time one-shot triggers when all of the following conditions are met: the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out.
On-Time One-Shot
The on-time of the one-shot is inversely proportional to the battery voltage as measured by the VP input, and directly proportional to the output voltage sensed at OUT: t ON = K x
The inductor current is never allowed to go negative. If the output voltage is above its regulation point and the inductor current reaches zero, the low-side driver is switched off. Once the output voltage falls below its regulation point, the high-side driver is switched on. This causes a dead time in between when the highside and low-side drivers are on, skipping pulses and resulting in the switching frequency slowing at light loads, thereby improving efficiency.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-size power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment where a large VBATT - VOUT differential exists. The highside driver (DH) is rated for 0.6A source/sink capability and swings from VP to GND. The low-side driver (DL) is
(VOUT + 0.075V)
VBATT
where K is internally fixed at 3.349s, and 0.075V is a factor that accounts for the expected drop across the synchronous switch. This arrangement maintains a switching frequency that is nearly constant as V BATT, ILOAD, and VOUT are changed. Table 3 shows the operating frequency range for the MAX1762/MAX1791. Note that the output voltage adjust range for continuous-conduction operation is restricted by the non12
Table 3. Operating Frequency
DEVICE MAX1762/MAX1791 K (s) 3.349 MIN (kHz) 268.7 TYP (kHz) 298.5 MAX (kHz) 328
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
i VBATT - VOUT = t L INDUCTOR CURRENT IPEAK IPEAK ILOAD INDUCTOR CURRENT
ILOAD = IPEAK/2
ILIMIT
0
ON-TIME
TIME
0
TIME
Figure 6. Pulse-Skipping/Discontinuous Crossover Point
Figure 7. "Valley" Current-Limit Threshold Point
rated for +0.5A, -0.9A source/sink capability and swings from VL to GND. The internal pulldown transistor that drives DL low is robust, with a 1 typical on-resistance. This helps prevent DL from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications, some combinations of high-and low-side FETS may cause excessive gate-drain coupling, which can lead to poor efficiency, EMI, and shoot-through currents. An adaptive dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully turned off. The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay.
sense voltage that appears at CS (Figure 8). Keep the impedance at this mode low to avoid errors at CS.
POR and Soft-Start
Power-on reset (POR) occurs when VBATT rises above approximately 2V, resetting the fault latch and soft-start counter and preparing the PWM for operation. UVLO circuitry inhibits switching until VVP rises above 4.1V, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. The ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after approximately 1.7ms.
Output Undervoltage Protection
The output UVLO function is similar to foldback current limiting but employs a timer rather than a variable current limit. The output undervoltage protection is enabled 20ms after POR or when coming out of shutdown. If the output is under 70% of the nominal value,
VP
Low-Side Current-Limit Sensing (ILIM)
The current-limit circuit employs a unique "valley" current-sensing algorithm that uses the on-state resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is below the current-limit threshold (-100mV from CS to GND), the PWM is not allowed to initiate a new cycle (Figure 7). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. If greater current-limit accuracy is desired, CS must be connected to the junction of the low-side switch source and a current-sense resistor to GND. The current limit will be 0.1V/RSENSE, and the accuracy will be 10%. A resistive voltage-divider from the inductor's switching mode to ground can be used to adjust the current-limit
DH 1.0k
MAX1762 MAX1791
CS 1.0k
VOUT
DL
Figure 8. Using a Resistive Voltage-Divider to Adjust CurrentLimit Sense Voltage to 200mV
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
then the PWM is latched off and does not restart until VP power is cycled, or SHDN is toggled low then high.
Design Procedure
Begin by establishing the input voltage range and maximum load current before choosing an inductor and its associated ripple-current ratio (LIR). The following four factors dictate the rest of the design: 1) Input voltage range. The maximum value (V VP (MAX) ) must accommodate the maximum AC adapter voltage. The minimum value (VVP(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum load current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stress and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stress and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit, ILOAD = ILOAD(MAX) x 0.8. 3) Switching frequency. The MAX1762/MAX1791 have a nominal switching frequency of 300kHz. 4) Inductor ripple-current ratio (LIR). LIR is the ratio of the peak-to-peak ripple current to the average inductor current. Size and efficiency trade-offs must be considered when setting the inductor ripple-current ratio. Low inductor values cause large ripple currents, resulting in the smallest size but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at critical conduction (where the inductor current just touches zero with every cycle). Inductor values lower than this grant no further size-reduction benefit. The MAX1762/MAX1791s' pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the load-current value at which switchover occurs. The optimum point is usually found between 20% and 50% ripple current. The inductor ripple current also impacts transientresponse performance, especially at low VVP - VOUT difference. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The
14
peak amplitude of the output transient (VSAG) is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
V (ILOAD(MAX) )2 x L K OUT + t OFF(MIN) VVP V -V 2 x COUT x VOUT K VP OUT - t OFF(MIN) VVP
VSAG =
where minimum off-time = 0.5s (max).
Inductor Selection
The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows: L= VOUT (VVP - VOUT ) VVP x x LIR x ILOAD(MAX)
Example: ILOAD(MAX) = 2A, VVP = 7V, VOUT = 1.6V, f = 300kHz, 35% ripple current or LIR = 0.35: L= 1.6V(7V -1.6V) = 5.9H 7 x 300kHz x 0.35 x 2A
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + [(LIR/2) ILOAD(MAX)]
Determining Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore: IVALLEY > ILOAD(MAX) - [(LIR/2) ILOAD(MAX)] where IVALLEY = minimum current-limit threshold voltage divided by the RDS(ON) of Q2. For the MAX1762/ MAX1791, the minimum current-limit threshold is 90mV. Use the worst-case maximum value for RDS(ON) from the MOSFET Q2 data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each C of temperature rise.
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks
Examining the 2A circuit example with a maximum RDS(ON) = 52m at +85C temperature reveals the following: IVALLEY = 90mV / 52m = 1.73A Checking the corresponding ILOAD(MAX) reveals: 1.73A I ILOAD(MAX) = VALLEY = = 2.1A 1 - 0.5 LIR 1 - 0.5 x 0.35 A current-sense resistor can be connected from CS to GND to set the current limit for the device. The MAX1762/MAX1791 use the sense resistor instead of the RDS(ON) of Q2 to limit the current. The maximum value of the sense resistor can be calculated with the equation: ILIMIT = 90mV / RSENSE once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG equation in the Design Procedure section). The amount of overshoot due to stored inductor energy can be calculated as: V LIPEAK 2 2CVOUT
MAX1762/MAX1791
where IPEAK is the peak inductor current.
Stability Considerations
Stability is determined by the value of the ESR zero (fESR) relative to the switching frequency (f). The point of instability is given by the following equation: ESR where: ESR 1 2 x x RESR x COUT
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VDIP ILOAD(MAX)
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR zero frequencies of 20kHz. In the design example used for inductor selection, the ESR needed to support a specified ripple voltage is found by the equation: RESR = VRIPPLE(p-p) LIR x ILOAD
where VDIP is the maximum tolerable transient voltage drop. In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple: RESR VP-P LIR x ILOAD(MAX)
where VP-P is the peak-to-peak output voltage ripple. The actual microfarad capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalum, SP, POS, and other electrolytic-type capacitors). When using low-capacity filter capacitors such as ceramics, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally,
where LIR is the inductor ripple current ratio, and ILOAD is the average DC load. Using a LIR = 0.35 and an average load current of 2A, the ESR needed to support 50mVP-P ripple is 71m. Do not use high-value ceramic capacitors directly across the fast feedback inputs (FB to GND) without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and FB pin. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This
15
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
"fools" the error comparator into triggering a new cycle immediately after the 500ns minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the MAX1762/MAX1791 EV kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under- or overshoot. duty cycle) equal to the switching losses (CV VP 2f). Make sure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. Conduction losses plus switching losses at the maximum input voltage should not exceed the package ratings or violate the overall thermal budget (see MOSFET Power Dissipation). In addition to efficiency considerations, the selection of the RDS(ON) of the low-side MOSFET must account for the regulator's required current limit. Choose a MOSFET that has a low enough resistance over the operating temperature range such that the device does not enter current limit during normal operation (see the Determining Current Limit section). Conversely, ultralow RDS(ON) devices may set the current limit too high and may result in only incremental improvements in efficiency. Some large n-channel FETs also have substantial interelectrode capacitance. Verify that the MAX1762/ MAX1791 DL driver can hold the gate off when the high side switch turns on. Cross-conduction problems can occur when the high-side switch turns on due to coupling through the n-channel's parasitic drainto-gate capacitance. The MAX1762/MAX1791 have adaptive dead-time circuitry that prevents the high-side and low-side MOSFETs from conducting at the same time (see MOSFET Gate Drivers). Even with this protection, it is still possible for delays internal to the MOSFET to prevent one MOSFET from turning off while the other is turned on. The maximum mismatch time that can be tolerated is 60ns. Select devices that have low turn-off times, and make sure that NFET(tD(off,max)) - PFET(tD(on,min)) < 60ns, and PFET(tD(off,max)) - NFET(tD(on,min)) < 60ns. Failure to do so may result in efficiency-killing shootthrough currents.
Input Capacitor Selection
The input capacitor must meet the ripple-current requirement (I RMS ) imposed by the switching currents. Nontantalum chemistries (ceramic or OS-CONTM) are preferred due to their resilience to power-up surge currents: VOUT (VVP - VOUT ) IRMS = ILOAD x VVP
Power MOSFET Selection
DC bias and output power considerations dominate the selection of the power MOSFETs used with the MAX1762/MAX1791. Take care not to exceed the device's maximum voltage ratings. In general, both switches are exposed to the supply voltage, so select MOSFETs with VDS (max) greater than VP (max). Gate drives to the n-channel and p-channel MOSFETs are not symmetrical. The n-channel device is driven from ground to the logic supply VL, while the p-channel device is driven from VP to ground. The maximum rating for VGS for the n-channel device is usually not an issue; however, VGS (max) for the p-channel must be at least VP (max). Since VGS (max) is usually lower than V DS (max), gate drive constraints often dictate the required p-channel breakdown rating. For moderate input-to-output differentials, the high-side MOSFET (Q1) can be sized smaller than the low-side MOSFET (Q2) without compromising efficiency. The high-side switch operates at a very low duty cycle under these conditions, so most conduction losses occur in Q2. For maximum efficiency, choose a highside MOSFET (Q1) that has conduction losses (I2R x
OS-CON is a trademark of Sanyo. 16
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation (PD) due to resistance occurs at minimum battery voltage: V PD(Q1 resistance) = OUT x ILOAD2 x RDS(ON) V VP(MIN) Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltage. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Again, the optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. High-
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks
side switching losses do not usually become an issue until the input is greater than approximately 15V. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum battery voltage is applied, due to the squared term in the CV2f switching loss equation. If the high-side MOSFET chosen for adequate R DS(ON) at low battery voltages becomes extraordinarily hot when subjected to VVP(MAX), reconsider your choice of high-side MOSFET. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on Q1: C RSS x VVP(MAX)2 x x ILOAD PD (Q1 switching) = IGATE where CRSS is the reverse transfer capacitance of Q1, and IGATE is the peak gate-drive source/sink current. For the low-side MOSFET, the worst-case power dissipation always occurs at maximum battery voltage: VOUT PD(Q2) = 1 x ILOAD2 x RDS VVP(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit must be overdesigned to tolerate: ILOAD = ILIMIT(HIGH) + (LIR / 2 ) ILOAD(MAX) where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFET must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. During the period when the high-side switch is off, current circulates from ground to the junction of both FETs and the inductor. As a consequence, the polarity of the switching node is negative with respect to ground. If unchanged, this voltage is approximately 0.7V (a diode drop) at both transition edges while both switches are off. In between the edges, the low-side switch conducts; the drop is IL RDS(ON). If a Schottky clamp is connected across the low-side switch, the initial and final voltage drops is reduced, improving efficiency slightly. Choose a Schottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency isn't critical.
MAX1762/MAX1791
Applications Issues
Dropout Performance
The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the t ON K-factor. Also, keep in mind that transient response performance of buck regulators operating close to dropout is poor, and bulk output capacitance must often be added. Dropout design example: VIN = 7V (min), VOUT = 5V, f = 300kHz. The required duty cycle is : V + VSW 5V + 0.1V DCREQ = OUT = = 0.74 VVP - VSW 7V - 0.1V The worst-case on-time is: V + 0.075 5V + 0.075 t ON(MIN) = OUT xK= x VVP 7V 3.35s x 90% = 2.18s The maximum IC duty factor based on timing constraints of the MAX1762/MAX1792 is: Duty = t ON(MIN) 2.18s = = 0.82, t ON(MIN) + t OFF(MAX) 2.18s + 0.5s
which meets the required duty cycle. Remember to include inductor resistance and MOSFET on-state voltage drops (VSW) when doing worst-case dropout dutyfactor calculations.
Fixed Output Voltages
The MAX1762/MAX1791 Dual Mode operation allows the selection of common voltages without requiring external components (Figure 9). Connect FB to GND for
17
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
OUT FIXED 1.8V FIXED 3.3V TO ERROR AMP
(Figure 10). Refer to the MAX1791 EV kit manual for a specific layout example. If possible, mount all of the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. Use a separate GND plane under OUT. Avoid the introduction of AC currents into the GND ground planes. Run the power plane ground currents on the top side only, if possible. Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. Inductor and GND connections to the synchronous rectifiers for current limiting must be made using Kelvin sensed connections to guarantee the current-limit accuracy. With 8-pin SO MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting GND and CS inside (underneath) the MAX package. When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Ensure that the OUT connection to COUT is short and direct. However, in some cases it may be desirable to deliberately introduce some trace length between the OUT connector node and the output filter capacitor (see Stability Considerations). Route high-speed switching nodes (CS, DH, and DL) away from sensitive analog areas (FB). Use GND as an EMI shield to keep radiated switching noise away from the IC's feedback divider and analog bypass capacitors.
FB 0.150V
MAX1762
2.5V
*
Figure 9. Feedback MUX
* a fixed +1.8V (MAX1762) or 3.3V (MAX1791) output. Connect FB to VL for a fixed 2.5V (MAX1762) or 5.0V (MAX1791) output. Otherwise, connect FB to a resistive voltage-divider for an adjustable output.
Setting the Output Voltage
Select VOUT > 1.25V for the MAX1762/MAX1791 by connecting FB to a resistive voltage-divider between V OUT and GND (Figure 2). Choose R2 to be about 10k, and solve for R1 using the equation: R1 VOUT = V FB x 1+ R2 where VFB = 1.25V. For a VOUT = 3.0V, R2 = 10k and R1 = 14k. For a desired VOUT < 1.25V, connect FB to a resistive voltage-divider between REF and OUT (Figure 3). Choose R1 to be about 50k, and solve for R2 using the equation: V -V R2 = OUT FB x R1 VFB - VREF where VFB = 1.25V and VREF = 2.0V. For a V OUT = 1.0V, R1 = 50k and R2 = 16.5k. Under these conditions, a minimum load of VREF - V FB / R1 >15A is required. * *
*
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially true when multiple converters are on the same PC board where one circuit can affect the other. The switching power stages require particular attention
18
*
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
USE AGND PLANE TO: USE PGND PLANE TO: - BYPASS VCC AND REF - BYPASS VVP - TERMINATE EXTERNAL FB - CONNECT PGND TO THE TOPSIDE STAR GROUND DIVIDER (IF USED) - PIN-STRAP CONTROL INPUTS AGND L1 PGND C2
D1
VOUT
P1 VL VIA TO GROUND VBATT CONNECT PGND TO AGND BENEATH THE MAX1762/MAX1791 AT ONE POINT ONLY AS SHOWN. NOTE: EXAMPLE SHOWN IS FOR DUAL n-CHANNEL MOSFET. C1 N1 GND
Figure 10. PC Board Layout Example
Layout Procedure
1) Place the power components first, with ground terminals adjacent (Q1 source, CIN, COUT). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the synchronous-rectifier MOSFETs, preferably on the back side in order to keep CS, GND, and the DL gate drive lines short and wide. The DL gate trace must be short and wide (measuring 50mils to 100mils wide if the MOSFET is 1in from the controller IC). 3) Place the VL bypass capacitor near the controller IC. 4) Make the DC-DC controller ground connections as follows: Near the IC, create a small analog ground plane. Connect this plane to GND, and use this plane for the ground connection for the REF and VVP bypass capacitors and FB dividers. 5) On the board's top side (power planes), make a star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection of the input capacitors, side 1 low-side MOSFET. Keep the resistance low between the star ground and the source of the low-side MOSFETs for accurate current limit. Connect the top-side star ground (used for MOSFET, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). 6) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias.
Chip Information
TRANSISTOR COUNT: 3520 PROCESS: S8E1FP
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High-Efficiency, 10-Pin MAX, Step-Down Controllers for Notebooks MAX1762/MAX1791
Package Information
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H
O0.500.1
0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
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